/*******************************************************************************
 *                                 AWorks
 *                       ----------------------------
 *                       innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * ALL rights reserved.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 *
 * The License of this software follows LGPL v2.1, See the LICENSE for more details:
 * https://opensource.org/licenses/LGPL-2.1
 *
 * Contact information:
 * web site:    http://www.zlg.cn/
 *******************************************************************************/
#ifndef __HPM_ROMAPI_XPI_NOR_DEF_H__
#define __HPM_ROMAPI_XPI_NOR_DEF_H__

/* \brief XPI NOR 属性定义*/
enum {
    xpi_nor_property_total_size,                        /* 总大小（字节） */
    xpi_nor_property_page_size,                         /* 页大小（字节）*/
    xpi_nor_property_sector_size,                       /* 扇区大小（字节） */
    xpi_nor_property_block_size,                        /* 块大小（字节） */
    xpi_nor_property_max = xpi_nor_property_block_size,
};

/* \brief 标准 XPI NOR 序列索引定义*/
typedef enum {
    xpi_std_nor_seq_idx_read             = 0U,  /* 0 - 读 */
    xpi_std_nor_seq_idx_page_program     = 1U,  /* 1 - 页编程 */
    xpi_std_nor_seq_idx_read_status      = 2U,  /* 2 - 读状态 */
    xpi_std_nor_seq_idx_read_status_xpi  = 3U,  /* 3 - xSPI 模式读状态 */
    xpi_std_nor_seq_idx_write_enable     = 4U,  /* 4 - 写使能 */
    xpi_std_nor_seq_idx_write_enable_xpi = 5U,  /* 5 - xSPI 模式写使能 */
    xpi_std_nor_seq_idx_erase_sector     = 6U,  /* 6 - 擦除扇区 */
    xpi_std_nor_seq_idx_erase_block      = 7U,  /* 7 - 擦除块 */
    xpi_std_nor_seq_idx_erase_chip       = 8U,  /* 8 - 擦除整个芯片 */
    xpi_std_nor_seq_idx_max              = 9U,  /* 9 */
} xpi_std_nor_instr_idx_t;

/* \brief 设备模式配置结构体*/
typedef struct {
    uint8_t cfg_cmd_type;  /* 配置命令类型 */
    uint8_t param_size;    /* 参数大小 */
} device_mode_cfg_t;

/* \brief XPI NOR 设备信息结构体*/
typedef struct {
    uint32_t          size_in_kbytes;                /**< Device Size in Kilobytes, offset 0x00 */
    uint16_t          page_size;                     /**< Page size, offset 0x04 */
    uint16_t          sector_size_kbytes;            /**< Sector size in kilobytes, offset 0x06 */
    uint16_t          block_size_kbytes;             /**< Block size in kilobytes, offset 0x08 */
    uint8_t           busy_offset;                   /**< Busy offset, offset 0x0a */
    uint8_t           busy_polarity;                 /**< Busy polarity, offset 0x0b */
    uint8_t           data_pads;                     /**< Device Size in Kilobytes, offset 0x0c */
    uint8_t           en_ddr_mode;                   /**< Enable DDR mode, offset 0x0d */
    uint8_t           clk_freq_for_device_cfg;       /**< Clk frequency for device configuration offset 0x0e */
    uint8_t           working_mode_por;              /**< Working mode after POR reset offset 0x0f */
    uint8_t           working_mode;                  /**< The device working mode, offset 0x10 */
    uint8_t           en_diff_clk;                   /**< Enable Differential clock, offset 0x11 */
    uint8_t           data_valid_time;               /**< Data valid time, in 0.1ns, offset 0x12 */
    uint8_t           en_half_clk_for_non_read_cmd;  /**< Enable half clock for non-read command, offset 0x13 */
    uint8_t           clk_freq_for_non_read_cmd;     /**< Enable safe clock for non-read command, offset 0x14 */
    uint8_t           dll_dly_target;                /**< XPI DLL Delay Target, offset 0x15 */
    uint8_t           io_voltage;                    /**< IO voltage, offset 0x16 */
    uint8_t           reserved0;                     /**< Reserved for future use, offset 0x17 */
    uint8_t           cs_hold_time;                  /**< CS hold time, 0 - default value, others - user specified value, offset 0x18 */
    uint8_t           cs_setup_time;                 /**< CS setup time, 0 - default value, others - user specified value, offset 0x19 */
    uint8_t           cs_interval;                   /**< CS interval, intervals between to CS active, offset 0x1a */
    uint8_t           en_dev_mode_cfg;               /**< Enable device mode configuration, offset 0x1b */
    uint32_t          flash_state_ctx;               /**< Flash state context, offset 0x1c  */
    device_mode_cfg_t mode_cfg_list[2];              /**< Mode configuration sequences, offset 0x20 */
    uint32_t          mode_cfg_param[2];             /**< Mode configuration parameters, offset 0x24 */
    uint32_t          reserved1;                     /**< Reserved for future use, offset 0x2C */
    struct {
        uint32_t      entry[4];
    } cfg_instr_seq[2];                              /**< Mode Configuration Instruction sequence, offset 0x30 */
} xpi_device_info_t;

/* \breif XPI NOR 配置结构体*/
typedef struct {
    uint32_t          tag;                               /**< Must be "XNOR", offset 0x000 */
    uint32_t          reserved0;                         /**< Reserved for future use, offset 0x004 */
    uint8_t           rxclk_src;                         /**< RXCLKSRC value, offset 0x008 */
    uint8_t           clk_freq;                          /**< Clock frequency, offset 0x009 */
    uint8_t           drive_strength;                    /**< Drive strength, offset 0x0a */
    uint8_t           column_addr_size;                  /**< Column address size, offset 0x0b */
    uint8_t           rxclk_src_for_init;                /**< RXCLKSRC during FLASH initialization, offset 0x0c */
    uint8_t           config_in_progress;                /**< Indicate whether device configuration is in progress, offset: 0x0d */
    uint8_t           reserved[2];                       /**< Reserved for future use, offset 0x00f */
    struct {
        uint8_t       enable;                            /**<  Port enable flag, 0 - not enabled, 1 - enabled */
        uint8_t       group;                             /**< 0 - 1st IO group, 1 - 2nd IO group */
        uint8_t       reserved[2];
    } chn_info[4];                                       /**< Device connection information */
    xpi_device_info_t device_info;                       /**< Device info, offset 0x20 */
    xpi_instr_seq_t   instr_set[xpi_std_nor_seq_idx_max];/**< Standard instruction sequence table, offset 0x70 */
} xpi_nor_config_t;

/**
 * @brief XPI NOR configuration option
 *        The ROM SW can detect the FLASH configuration based on the following structure specified by the end-user
 */
typedef struct {
    union {
        struct {
            uint32_t words: 4;       /**< Option words, exclude the header itself */
            uint32_t reserved: 8;    /**< Reserved for future use */
            uint32_t tag: 20;        /**< Must be 0xfcf90 */
        };
        uint32_t U;
    } header;
    union {
        struct {
            uint32_t freq_opt: 4;                /**< 1 - 30MHz, others, SoC specific setting */
            uint32_t misc: 4;                    /**< Not used for now */
            uint32_t dummy_cycles: 8;            /**< 0 - Auto detected/ use predefined value, others - specified by end-user */
            uint32_t quad_enable_seq: 4;         /**< See the xpi_nor_quad_enable_seq_t definitions for more details */
            uint32_t cmd_pads_after_init: 4;     /**< See the xpi_data_pad_t definitions for more details */
            uint32_t cmd_pads_after_por: 4;      /**< See the xpi_data_pad_t definitions for more details */
            uint32_t probe_type: 4;              /**< See the xpi_nor_probe_t definitions for more details */
        };
        uint32_t U;
    } option0;
    union {
        struct {
            uint32_t drive_strength: 8;      /**< IO drive strength, 0 - pre-defined, Others - specified by end-user */
            uint32_t connection_sel: 4;      /**< Device connection selection: 0 - PORTA, 1 - PORTB, 2 - Parallel mode */
            uint32_t pin_group_sel: 4;       /**< Pin group selection, 0 - 1st group, 1 - 2nd group, by default, the pin group is 1st group */
            uint32_t io_voltage: 4;          /**< SoC pad voltage, 0 - 3.0V, 1-1.8V */
            uint32_t reserved: 12;           /**< Reserved for future use */
        };
        uint32_t U;
    } option1;
    union {
        struct {
            uint32_t flash_size_option:8;               /**< FLASH size option */
            uint32_t flash_sector_size_option:4;        /**< FLASH sector size option */
            uint32_t flash_sector_erase_cmd_option:4;   /**< Sector Erase command option */
            uint32_t reserved:20;
        };
        uint32_t U;
    } option2;
} xpi_nor_config_option_t;

#endif
